I. Field of the Invention
The present invention relates generally to memory devices and particularly to single partition flash memory devices.
II. Description of the Related Art
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include portable computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code, system data such as a basic input/output system (BIOS), and other firmware can typically be stored in flash memory devices.
A single partition flash memory device has only one internal write charge pump. Therefore, writing data to the device, also referred to as programming, puts it into a busy state such that data cannot be read from it during the write operation. If a read operation is performed during the busy state, a logical 00 is typically returned. The busy state for a write operation may last 8–12 microseconds.
Similarly, initiating an erase operation of the flash memory device puts the memory device into the busy state. The device typically enters the busy state for 0.50–1.0 second during an erase operation. During this time, the device is not accessible.
Lack of accessibility during write and erase operations may cause a system using the flash memory device to operate slower than normal. The processor that is attempting to read the contents of the flash device must wait until the write or erase operations are complete before being able to obtain the desired data. There is a resulting need in the art for a single partition flash memory device, having multiple banks and device configurations, that permits a read operation during a write or erase operation.